Digital System Clocking: High-Performance and Low-Power Aspects

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Digital System Clocking: High-Performance and Low-Power Aspects

Vojin G. Oklobdzija,Vladimir M. Stojanovic,Dejan M. Markovic,Nikola M. Nedovic

Description

Digital System Clocking is assuming ever greater importance as clock speeds increase, doubling every three years. This—the first book to focus entirely on clocked storage elements, "Flip-Flops" or "Latches"—provides an in-depth introduction to the subject for both professional computer design engineers and graduate-level computer engineering students. In Digital System Clocking: High-Performance and Low-Power Aspects, you will find information on:

Clocking in synchronous systems including on-chip clock generation, timing parameters, and clock signal distribution
Latch-based and Flip-Flop derivation
Clock-to-output delay tcq
Pipelining and timing analysis
Absorbing clock uncertaintites and dynamic time borrowing
Low-swing circuit techniques, clock gating, and dual-edge triggering
Simulation techniques including HLFF and M-SAFF sizing and CSE simulation bench in SPICE
Clocked storage elements in CMOS technology
The associated website provides materials for Instructors

With numerous microprocessor examples including clocking for Intel®, Sun Microsystems’s UltraSPARC®-III, and IBM processors, Digital System Clocking: High-Performance and Low-Power Aspects provides much-needed answers about a technology that stands as a centerpiece of digital system design.

About the Author

VOJIN G. OKLOBDZIJA received his PhD from the University of California, Los Angeles. He has been a consultant for major computer and electronics companies in the fields of high-performance systems, low-power design, and fast data-path implementations with the emphasis on multi-media applications and has published extensively on the subjects of system design and computer engineering. Dr. Oklobdzija has worked at the IBM T.J. Watson Research Center where he did pioneering work on RISC architecture and machine development starting with the IBM 801. Currently, he is a professor in the Department of Electrical and Computer Engineering at the University of California, Davis, where he directs the Advanced Computer Systems Engineering Laboratory (ACSEL).

VLADIMIR M. STOJANOVIC is currently pursuing his PhD degree as a member of the VLSI research group, Electrical Engineering Department, Stanford University. He obtained MSEE degree from Stanford University and Dipl Ing diploma from Faculty of Electrical Engineering, University of Belgrade, Serbia. He was a research scholar at ACSEL.

DEJAN M. MARKOVIC received an Dipl Ing degree in Electrical Engineering from the University of Belgrade, Yugoslavia, in 1998 and an MS in Electrical Engineering from the University of California at Berkeley in 2000, where he is currently working toward a PhD. Mr. Markovic received the 2000-2001 CalVIEW Fellow Award for excellence in teaching and mentoring of industry engineers through the UC Berkeley distant learning program. He is a current member of the UC Berkeley Hitachi Fellow Team, conducting market research on Hitachi?s Mu-Chip RFID technology.

NIKOLA NEDOVIC is currently pursuing his PhD in the Department of Electrical and Computer Engineering at the University of California, Davis. He was a research scholar at ACSEL, and has been published in seven papers.

Series

IEEE Press

To Purchase this product, please visit

https://dev.store.wiley.com/en-ca/Digital+System+Clocking%3A+High-Performance+and+Low-Power+Aspects-p-9780471723684